Senior Engineer - SoC Design Engineering

Experience: 5 to 12 years

Location: Pune, Maharashtra, India

Skills: ARM-based microcontrollers, low-power design techniques, RTL coding, debugging, design reviews, Lint, CDC, LowPower design, CLP, Timing optimization, EDA tools, Synopsys, Cadence, SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI, Flash memory, PSRAMs, cryptographic accelerators, security IPs, Analog IPs, ADC, DAC, PLLs, LDOs

Role Overview
We are seeking an experienced System-on-Chip (SoC) Digital Design engineer with 5-12 years of expertise for execution of advanced SoCs for embedded applications. The ideal candidate will have strong experience in ARM-based microcontrollers, low-power design techniques, and proficiency with multiple interfaces and security IPs. This is a hands-on role requiring strong technical expertise and collaboration in a fast-paced environment.

Key Responsibilities
Develop and own various SoC & subsystem design activities, including CPU subsystems, interconnects, and memory hierarchy, IP design/updates, optimizations, low power design etc.
• Hands-on design work: RTL coding, debugging and design reviews.
• Execute various RTL design related activities including Lint/CDC/LowPower design/CLP/Timing optimization etc for advanced SoCs.
• Collaborate with cross-functional teams like DV/Synthesis/DFT/PhysicalDesign and Software integration.
• Collaborate with teams in developing and improving flows for maximum reuse and efficiency.




• Mentor junior team members while actively collaborating with other teams for issue resolutions and sign-off.
• Ensure PPA optimization and compliance with industry standards.

Required Qualifications
Experience:
5-12 years in SoC design and participation with successful tape-outs of SoCs.
Technical Skills:
Strong expertise in ARM-based microcontrollers and SoC integration and excellent debugging skills.
• Proficiency in RTL (Verilog/SystemVerilog), synthesis, timing closure.
• Comfortable working with Synthesis/STA/Physical Design/Package teams during SoC design.
• Familiarity with EDA tools (Synopsys, Cadence).
• Familiarity / Knowledge of low-power design techniques.
• Experience with multiple interfaces like SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI.
• Knowledge of various off-chip memory technologies like Flash memory, PSRAMs etc.
• Additional experience with cryptographic accelerators or security IPs.
• Familiarity with common Analog IPs used in microcontroller design (e.g., ADC, DAC, PLLs, LDOs) is a plus.
Soft Skills:
Comfortable working in a fast-paced environment.
• Enthusiastic and solid team player, keen desire to learn new technologies convert ideas into reality and excellent communication skills.

Education
Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering
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📌 Senior Engineer SoC Design Engineering (Pune)
🏢 NXP Semiconductors
📍 Pune