Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Develop RTL for multiple logic blocks and understanding supporting Existing highspeed RTL design
Run various frontend tools to check for linting, clock domain crossing, synthesis, etc.
Work with verification team to collaborate on test plan, coverage plan, and coverage closure.

Job Function

This position is for RTL designer role in CSI team working on RTL. The position involves in-depth understanding of the ASIC design flow from RTL to synth/PD and the challenges posed by advanced technologies.



The successful candidate will possess detailed understanding of RTL design, synthesis(would be a plus). Knowledge and experience of handling HighSpeed IP's is a definite advantage.

Skills/Experience
Must have 5 to 8 years of practical experience with details of RTL development (VHDL or Verilog or system verilog ) including:
functional and structural RTL design, design partitioning and Micor Architecture Doc
simulation and regression, collaboration with design verification team. Must have valuable familiarity with latest RTL languages.
including: simulation systems (e.g. Modelsim, VCS), Linting (Spyglass) and CDC (spyglass)
Exposure in synthesis tools (e.g. Design Compile) and Timing (PT) and System Verilog Assertion, etc.
Experience with the following area is highly desirable:
Solid RTL design, architecture knowledge, CDC and Linting Experience
Microarchitecture Planning and Low power design

📌 Rtl Design Engineer, Sr Lead Bengaluru
🏢 Qualcomm
📍 Bengaluru