Job Description

Looking for a 12+ years experienced Engineering Manager with in-depth understanding of Analog concepts, experience of design of complex Analog I/Ps & sub-blocks, integrating I/Ps and sub systems and ownership, experience of fully owning smaller ICs (Point of loads, Single Converters) and owning major I/Ps in large PMICs, to join the 2.6B$ Power Business Unit. The candidate will get to work on a wide range of exciting products such as PMICs, Linear and Switching DC-DC converters powering the next generation of Renesas processors. This is an early-stage growth chance where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio.

Essential Functions:

- Must be proficient in designing and owning complex I/Ps like +ve/-ve Charge Pumps, Buck Converters, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc.

- Must have in-depth Understanding of and should be able to implement & compensate the Control Loops, Analog feedback loops and should know trade-offs between various compensation strategies.

- Should be able to build/support Block level spec break down from Top level chip requirements and independently own, design complete switching converter e.g. Buck, Boost, Buck-Boost etc and LDOs. Must be able to do block level error budgeting depending on the block requirements.





- Must be aware of relative differences of various control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and decide/implement the best option to meet converter level performance specifications and other system requirements.

- Must be able to bring in innovative ideas to improve designs to meet challenging specifications.

- Should have in-depth knowledge of Analog layouts and be able to work closely with layout lead from floor planning till Chip Top completion and verification and do trade-offs based on desired performance

- Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges.

- Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success.

- Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy.

- Should have experience of end-to-end IC development flow, Silicon debugs, and taking ICs to production

- Should be able to lead/manage a small group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs.

- Should have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC

📌 Senior Staff Engineer, Analog Design (Bengaluru)
🏢 renesas electronics
📍 Bengaluru