Senior Design Verification Engineer (7 -18 Years)

Location: Pune | Notice Period: 45-60 days (Serving notice period only)

Responsibilities & Requirements

- Leadership: Lead a 56 member DV team while driving full ASIC/SoC verification from concept to tape-out.
- Architecture & Planning: Create IP and sub-system verification plans, testbenches (TB), sequences, and portable verification infrastructure.
- UVM Integration: Build reusable SystemVerilog/UVM environments; integrate multi-instance VIPs at the SoC level.
- High-Speed & Bus Protocols: Hands-on experience verifying PCIe, Ethernet, USB, and AMBA bus architectures.
- Low-Power & HW/FW: Expertise in UPF integration, boot-up, power-cycling, and verifying firmware/hardware interactions.
- Cross-Functional Ownership: Collaborate with Design, SW/FW, and Architecture teams to hit coverage targets and ensure tape-out readiness.
- Qualifications: BS/MS in EE/CS; 8+ years total DV experience with 2+ years leading complex IP verification.

📌 Lead Verification Engineer (Pune)
🏢 ACL Digital
📍 Pune