Category EngineeringHire Type EmployeeJob ID 12343Remote Eligible NoDate Posted 23 07 2025 Alternate Job Titles ASIC Physical Design Engineer Place Route Engineer Sr Physical Design Specialist We Are At Synopsys we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence from self-driving cars to learning machines We lead in chip design verification and IP integration empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation You Are You are a passionate and detail-oriented engineer with a strong background in ASIC physical design and a keen interest in advancing semiconductor technology You thrive in collaborative fast-paced environments and are motivated by technical challenges that push the boundaries of what s possible in chip design With your foundational education in electronics or electrical engineering you have honed a solid understanding of CMOS and submicron ASIC flows working on advanced technology nodes such as 28nm 16nm 14nm 10nm and 7nm You possess hands-on experience with industry-leading EDA tools including Synopsys ICC-II FC Design Compiler PrimeTime and Cadence Innovus and are adept at developing optimizing and verifying robust ASIC design flows Your curiosity drives you to stay on top of the latest methodologies and your analytical mindset ensures you can solve complex problems with cutting-edge solutions You are comfortable taking ownership of tasks whether it s developing flows performing timing analysis or releasing production views for IP You communicate clearly collaborate effectively and are committed to delivering high-quality results with attention to every detail You believe in continuous improvement proactively seeking ways to optimize power performance and area PPA while maintaining the highest standards of quality Most importantly you are excited about making an impact in a global team that values diversity learning and technological excellence What You ll Be Doing Developing and optimizing ASIC design flows to build and verify standard cell libraries ensuring the best possible Power Performance and Area PPA with uncompromised quality Creating and maintaining Place Route P R methodologies using industry-standard tools such as Synopsys ICC-II FC and Cadence Innovus Releasing P R production views for IP ensuring readiness for downstream design and integration teams Conducting thorough physical verification DRC LVS timing analysis STA and addressing design closure challenges across advanced technology nodes Collaborating with cross-functional teams to integrate design flows improve automation and resolve technical issues throughout the ASIC lifecycle Implementing and validating low-power design concepts using UPF CPF formats and ensuring robust power analysis and planning Generating and managing technology files library views Milkyway NDM and deliverables such as LEF DEF GDS for standard cell libraries The Impact You Will Have Enable the creation of high-performance energy-efficient silicon chips that power next-generation applications and devices Drive improvements in PPA and overall design quality directly influencing customer satisfaction and product competitiveness Ensure timely and robust release of IP production views accelerating time-to-market for Synopsys customers Advance the state-of-the-art in physical design methodologies contributing to Synopsys leadership in the semiconductor industry Collaborate cross-functionally to