What You ll Do

- Architect, model, and implement digital PID / cascade control loops (voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs operating at 10 100 MHz.

- Develop high-fidelity plant models in MATLAB / Simulink (averaged and switched models) using extracted parasitics from Ansys Q3D / SIwave (inductor matrices, PDN impedance, frequency-dependent losses).

- Perform closed-loop stability analysis on switched power stages.

- Translate validated MATLAB/Simulink controller models into production-quality RTL (Verilog / SystemVerilog) using HDL Coder or manual high-quality coding.

- Design and implement supporting digital blocks: ADC interface, DPWM (digital PWM).

- Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting.





- Perform mixed-signal verification: co-simulation of RTL (VCS / Xcelium) with analog models (Spectre / APS) and behavioral models (Simulink / SIMPLIS / PLECS).

- Analyze and optimize for area, power, timing, and metastability in the digital controller across PVT corners.

- Support silicon bring-up, debug, and controller tuning on lab hardware.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Mixed-Signal Design RTL Design Engineer (Bengaluru)
🏢 tylsemi
📍 Bengaluru