Senior Technical Architect - Design Validation

Experience: Not Available to Not Available years

Location: Bangalore, India

Skills: C, SystemVerilog, UVM, Debugging, RISC-V, ARM, ASIC IP-level verification

Job Summary
15 years of experience in Design verification

Key Responsibilities
• Develop and review C-based tests / reference models integrated with SV/UVM environments
• Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
• Test planning, execution, and closure at IP level
• Writing and debugging constraint-random tests
• Development and analysis of functional coverage and code coverage
Skill Requirements
• Experience in Subsystem verification with CPU driven tests
• Experience in RISC-V based CPU environment
• ARM system IP and debug IP experience
• ASIC IP-level verification using SystemVerilog and UVM
• Solid Debugging Skills
Other Requirements
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📌 Senior Technical Architect Design Validation (Bengaluru)
🏢 HCL Technologies
📍 Bengaluru