07 Aug
|
Shervani Tech Hub
|
India
07 Aug
Shervani Tech Hub
India
Key Responsibilities
Develop and execute comprehensive verification plans for PCIe IP/Subsystems.
Build and maintain reusable UVM-based verification settings.
Create test cases, sequences, scoreboards, assertions, and coverage models.
Verify PCIe Gen3/Gen4/Gen5 (Gen6 is an advantage) compliance and functionality.
Perform protocol, functional, and regression testing.
Analyze simulation results, debug RTL issues, and collaborate with design engineers to resolve bugs.
Drive functional and code coverage closure.
Develop constrained-random and directed test scenarios.
Participate in design reviews and verification sign-off activities.
Work closely with architecture, RTL, firmware, and validation teams throughout the development lifecycle.
📌 Design Verification Engineer Pcie Bengaluru (India)
🏢 Shervani Tech Hub
📍 India