1) Staff / Principal Engineer - Verification ( OVM / UVM), DDR - [ID 014]

Job Description

Hands on project experience with leading edge verification methodologies like OVM/UVM
Domain experience of DDR3/DDR4/LPDDR3/LPDDR4 is must
Hands on project experience in verifying projects using DDR2/DDR3 protocols
Hands on project experience in coverage/assertion driven verification
Knowledge of IC chip design, development flow, process, and methodology
Knowledge of CMOS logic design, circuit design, and circuit analysis
Proficient in HDL languages SystemVerilog, Verilog and VHDL
Valuable knowledge of UNIX shell scripting, Perl and TCL scripting.
Proven experience in writing verification plans and test bench development , simulation, and debugging

Skills:

Verification, OVM/UVM, DDR/PCIe, System Verilog

Job Location:

Bangalore | Hyderabad | Pune | Noida

Experience:

8 - 18 Years

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📌 Staff / Principal Engineer Verification Pune (India)
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