Role & responsibilities

We are seeking an experienced Design for Testability (DFT) Engineer to join our ASIC/SoC design team. In this role, you will be responsible for defining and implementing DFT strategies, integrating test architectures, generating manufacturing test patterns, and supporting silicon bring-up for complex, high-performance SoCs and ASICs.

You will work closely with RTL Design, Design Verification, Physical Design, STA, and Product Engineering teams to ensure high manufacturing test quality, maximize fault coverage, minimize test time, and optimize overall test costs.

Key Responsibilities
Develop and implement Design for Test (DFT) methodologies for complex ASIC and SoC designs.
Participate in the complete DFT implementation flow from planning to silicon validation.
Define and execute DFT architecture, ensuring high fault coverage and productive testability.
Perform Scan Planning, Scan Insertion, Scan Stitching, and Scan Chain Verification.
Plan, insert, and validate Memory Built-In Self-Test (MBIST) architecture for embedded memories.
Perform Partitioning of SoC designs for effective scan implementation and improved testability.




Implement and verify Test Compression techniques to reduce tester memory and test application time.
Perform Wrapper Insertion for IPs and SoCs to support hierarchical DFT implementation.
Generate high-quality ATPG (Automatic Test Pattern Generation) patterns for stuck-at, transition, and other structural faults.
Execute ATPG simulations and analyze coverage reports to achieve targeted fault coverage.
Handle both Flat and Hierarchical SoC DFT implementations across large-scale designs.
Develop and validate JTAG (IEEE 1149.1) and Boundary Scan architecture for board-level testing and device debugging.
Create and validate STA timing constraints for DFT modes, including scan shift, scan capture, MBIST, and JTAG operations.
Collaborate with Physical Design teams to ensure DFT logic is implemented efficiently with minimal timing and routing impact.
Support silicon bring-up, manufacturing test debugging, and failure analysis.
Work closely with cross-functional teams including RTL, Verification, Physical Design, Product Engineering, and Test Engineering throughout the product lifecycle.

Preferred candidate profile

📌 Dft Design Engineer Bengaluru
🏢 Sykatiya Technologies
📍 Bengaluru