VLSI Physical Design Engineer (12-Month Contract)

Location: Bangalore

Experience: 4+ Years

Employment Type: 12-Month Contract

Job Responsibilities:

Execute the complete RTL-to-GDSII Physical Design flow.

Perform Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Sign-off.

Analyze and resolve timing, congestion, and power-related issues to achieve PPA targets.

Perform sign-off verification including Static Timing Analysis (STA), DRC, LVS, and PEX.

Work with standard cell libraries and EDA views such as LIB, LEF, NDM, CDL, and GDS.

Collaborate with cross-functional teams to ensure successful chip implementation.

Required Skills:

4+ years of experience in VLSI Physical Design.





Solid knowledge of RTL-to-GDSII Physical Design flow.

Hands-on experience in Floorplanning, Placement, CTS, Routing, and Physical Sign-off.

Experience with STA, DRC, LVS, and PEX.

Hands-on experience with Synopsys ICC2 and/or Cadence Innovus.

Understanding of PPA (Power, Performance, Area) optimization.

Experience working on advanced technology nodes such as 22nm, 16nm, or 5nm.

Robust debugging and problem-solving skills.

Qualification:

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.

📌 Physical Design Engineer Bengaluru
🏢 Allegis Global Solutions (AGS)
📍 Bengaluru