07 Aug
|
SmartSoC Solutions
|
India
07 Aug
SmartSoC Solutions
India
Required Skills
Robust understanding of the complete ASIC Physical Design flow.
Hands-on experience with DDR3/DDR4/DDR5 or LPDDR PHY hardening.
Expertise in floorplanning, placement, CTS, routing, timing closure, and ECO implementation.
Robust knowledge of Static Timing Analysis (STA), MMMC, OCV/AOCV/POCV, and CRPR.
Experience with signal integrity, crosstalk, IR drop, and EM analysis.
Knowledge of physical verification, including DRC, LVS, and antenna checks.
Proficiency in Tcl, Python, Perl, or Shell scripting.
Excellent debugging, analytical, and problem-solving skills.
5+ years of relevant experience in physical design.
📌 Physical Design Engineer Bengaluru (India)
🏢 SmartSoC Solutions
📍 India