Develop RTL designs using Verilog/System Verilog based on architecture and design specifications.
Create and execute test plans, testcases, and verification settings for validating RTL functionality.
Perform module-level and subsystem-level design, integration, simulation, and debugging.
Analyze simulation results, debug design and verification issues, and drive them to closure.
Work closely with design, verification, FPGA, and system teams to ensure quality deliverables.
Participate in design reviews, code reviews, and verification reviews.
Support synthesis, FPGA prototyping, coverage closure, and regression activities as required.
Prepare and maintain the design and verification of documentation.

Required Skills & Experience:




Strong understanding of digital design fundamentals, computer architecture, and hardware design concepts.
Hands-on experience in Verilog/System Verilog.
Valuable understanding of RTL design concepts, FSMs, synchronous design, and timing fundamentals.
Knowledge of verification methodologies, simulation, debugging, and functional coverage concepts.
Familiarity with standard bus protocols such as AXI, APB, AHB, PCIe, DDR, or Ethernet is an advantage.
Strong analytical, debugging, and problem-solving skills.
Positive communication and teamwork abilities.

📌 Rtl Verification/design Hyderabad (India)
🏢 Tata Elxsi
📍 India