Hands-on experience in AMD Tile Builder flow for block and full-chip implementations.
Solid expertise in RTL-to-GDSII flow including Synthesis, Floor planning, P&R;, STA, EMIR, and Signoff.
Experience on TSMC N6/N5/N4/N3/N2P technologies.
Required Candidate profile
Experience with Full-Chip Floor planning, partitioning, macro/IO placement, power planning, and hierarchical integration.
Expertise in Full-Chip Timing Closure, MCMM analysis, timing signoff,
📌 Lead Physical Design Engineer Bengaluru
🏢 Nippon Data Systems
📍 Bengaluru
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.