Experience: 5 to 12 Years
Location: Bangalore | Hyderabad | Pune | Noida | Ahmedabad | Chennai
Role Summary
We are seeking a hands-on ASIC RTL Design Engineer with solid expertise in RTL design and SoC development. The ideal candidate should have experience in designing high-quality, synthesizable RTL for complex ASIC/SoC projects.
Key Responsibilities
Develop RTL using Verilog/SystemVerilog based on architectural specifications.
Perform microarchitecture design, RTL coding, and SoC/IP integration.
Collaborate with Verification, DFT, Physical Design, and Architecture teams.
Support synthesis, lint, CDC, timing closure, and silicon bring-up.
Participate in design reviews and technical discussions.
Required Skills
Solid RTL design experience using Verilog/SystemVerilog.
Valuable understanding of digital design fundamentals and ASIC design flow.
Experience with synthesis, lint, CDC, and STA concepts.
Knowledge of AMBA protocols (AXI/AHB/APB) is preferred.
Scripting in TCL, Python, Perl, or Shell is an added advantage.