10 Aug
|
Marvell Technology
|
Hyderabad
10 Aug
Marvell Technology
Hyderabad
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Principal Engineer, Design For Test at Marvell, you'll be a recognized DFT technical authority within the Custom Silicon Engineering team — a leader in large multi-die designs driving high compute performance and acceleration in custom AI and XPU markets. The role is challenging and requires an experienced DFT engineer who can work with existing solutions while creating new methodologies to address industry-first test challenges on the most advanced process nodes.
What You Can Expect
- Architect, lead,
and implement DFT/Test on complex IP and SoC for multiple custom/compute/XPU ASIC/SoC designs across 3nm, 2nm, and emerging process nodes.
- Drive DFT architecture definition and own implementation of DFT/DFX features including scan, MBIST/BIRA/BISR, IJTAG, OCC, EDT compression, ATPG (SAF/TDF/NPSF), and post-silicon bring-up.
- Lead DFT execution from RTL through mass production readiness (MPR): insertion, validation, STA, pattern generation, ATE handoff, and silicon debug.
- Define and enhance DFT methodologies and tool flows; benchmark new approaches and enable next-generation methodology in the M1DPx Tessent-based setting.
- Mentor and guide a team of Staff and Senior Staff DFT engineers, enabling them to scale across multiple concurrent designs.
- Collaborate closely with Physical Design, timing closure, and product engineering teams on DFT physical implementation, scan chain optimiza
📌 Principal Engineer, Design For Test (Hyderabad)
🏢 Marvell Technology
📍 Hyderabad