VHDL/FPGA Design Engineer

Job responsibilities

 Designing high-performance digital blocks for Complex Communication Coding using VHDL.

 Hands-on with RTL development (VHDL), simulation, writing test benches, and debug.

 Experience with developing timing constraints and running state-of-the-art synthesis tools, timing analysis tools, such as Xilinx Vivado suite.

 Participate in module architecture and specification.

 Blocklevel design verification  Solid hands-on with RTL development (VHDL), simulation, writing test benches, and debug.

 Experience with developing timing constraints and running state-of-the-art synthesis tools, timing analysis tools, such as Xilinx Vivado suite.

 Must have worked on top-level SoC integrated processor cores with standard peripherals.

 Must have exposure to communication protocols.

 Should be very positive in the debugging the HDL codes, and be able to make progress by identifying and fixing the issues/bugs in the design.

 Positive knowledge in SoC architecture, such as Xilinx Zynq SoC.

Pay: ₹1,000,000.00 - ₹1,200,000.00 per year

Benefits
Health insurance
Life insurance
Provident Fund

Work Location: In person

📌 Vhdl Design Engineer Jubilee Hills
🏢 Puneriyas Entertainment
📍 Jubilee Hills