Hiring: VLSI / ASIC Design Engineers Intern

We are looking for talented VLSI Engineers to join our team across ASIC Frontend, RTL Design, and Backend / Physical Design.

ASIC Frontend Engineer
Skills Required:
ASIC Frontend Design
RTL Coding
Verilog
UVM
RTL Design & Verification
Valuable understanding of digital design concepts

Backend / Physical Design Engineer
Skills Required:
DFT/ physical design
Backend VLSI flow
RTL-to-GDSII flow
Physical Design implementation
Understanding of PnR, timing, and physical verification flows

Flow / Automation Engineer
Skills Required:
VLSI flow development and automation
RTL-to-GDSII flow knowledge
Python and/or TCL scripting
Module-level flow automation
Development and integration of ASIC design flows




Positive understanding of Frontend-to-Backend design flow
Key Skills

Frontend: ASIC Frontend, RTL Coding, Verilog, UVM

Backend: Physical Design, BFT, RTL-to-GDSII

Automation: Python, TCL, Flow Development
Why Join Us?
Work on real-world ASIC/VLSI projects
Exposure to complete RTL-to-GDSII design flow
Prospect to work across Frontend, Backend, and Flow Development
Learn and work with industry-standard VLSI methodologies and tools
Interested candidates can share their updated resume with us.

Pay: From ₹35,000.00 per month

Work Location: In person

📌 Vlsi / Asic Design Engineers Intern Ahmedabad
🏢 SoftRefine Technology
📍 Ahmedabad