? Hiring: Physical Design Engineer (ASIC)

? Location: Bangalore

? Experience: 1.5 – 4 Years

? Budget: 30–40% hike on current CTC

â±ï¸ Notice Period: Immediate joiners preferred

? Role Overview

We are looking for a Physical Design Engineer with hands-on experience in RTL-to-GDSII ASIC implementation across advanced nodes. You will work on high-performance chip design and contribute to full-cycle physical implementation and signoff.

? Key Skills
RTL to GDSII Flow: Floorplanning, Placement, CTS, Routing
Timing: STA, MCMM/MMMC timing closure, ECO implementation
Tools: Synopsys ICC2, PrimeTime, Design Compiler
Signoff: DRC/LVS debugging, physical verification
Optimization: PPA (Performance, Power, Area) improvements
Low Power: Power planning, IR drop, clock optimization

â Requirements
1.7+ years of experience in Physical Design (ASIC)
Robust understanding of timing closure & backend flow
Experience in advanced nodes (14nm or similar preferred)
Valuable collaboration with RTL & STA teams

? Why Join
Work on cutting-edge semiconductor designs
Exposure to advanced node technologies
Growth-focused, high-impact engineering setting

📌 Physical Design Engineer Bengaluru (India)
🏢 Vrinda International
📍 India