? Required Experience

- 5+ years of hands-on ASIC / SoC Design Verification experience

- Robust experience with

SystemVerilog & UVM

- Hands-on verification experience in any one or more of the following protocols:

- ?

PCIe / PCI Express

- ?

DDR / LPDDR

- ?

MIPI

- ?

SerDes

- ?

USB

- ?

Ethernet

- ?

CXL

- ?

UCIe

- ?

High-Speed Interconnect / Data Transfer Protocols

? Key Responsibilities

- Develop and execute functional verification strategies for complex ASIC/SoC designs.

- Develop

SystemVerilog/UVM testbenches

, test scenarios and verification environments.

- Create test plans, test cases, functional coverage and assertions

.

- Perform debugging and root-cause analysis using simulation and waveform tools.

- Work closely with

RTL Design, Architecture and SoC teams to identify and resolve design issues.

- Drive verification from test planning through coverage closure and sign-off

.

- Participate in

IP, subsystem and SoC-level verification

.

📌 Senior Design Verification Engineer (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru