This role is for one of our clients
Industry: Semiconductors

Seniority level: Mid-Senior level

Min Experience: 6+ years

Location: Bengaluru

JobType: full-time

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We are seeking an experienced
Physical Design Engineer
with
6–15 years of industry experience
to join our VLSI/ASIC engineering team. The ideal candidate will have robust hands-on expertise across the physical implementation flow, with particular emphasis on
Cadence Innovus
and
Static Timing Analysis (STA)
. You will be responsible for taking designs from netlist through physical implementation, optimization,



timing closure, and sign-off while working closely with RTL, synthesis, STA, and verification teams.

Requirements
Key Responsibilities
- Perform end-to-end physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification
- Develop and implement physical design strategies for complex digital blocks and full-chip designs
- Use Cadence Innovus extensively for placement, CTS, routing, timing optimization, and design closure
- Analyze timing reports and perform STA to identify setup and hold violations and drive timing closure
- Work on congestion analysis, placement optimization, buffering, cell sizing, and other techniques to improve PPA and timing
- Perform clock-tree analysis and optimization to manage skew, latency, transition, and clock-related constraints
- Collaborate with synthesis and RTL teams to resolve timing,

📌 Physical Design Engineer (Bengaluru)
🏢 Weekday (YC W21)
📍 Bengaluru