Powering the next wave of AI infrastructure. Tsavorite builds next-generation AI compute systems for edge, on-prem, and data centre deployments. The company is developing a heterogeneous, chiplet-based architecture that combines custom AI Cores, ARM Application Cores, high-bandwidth memory, and the MultiPlexus™ scalable fabric to support inference, training, and emerging agentic AI workflows. Delivered through the Helix platform and TAOS software stack, Tsavorite has design centres in the US and India. Tsavorite's systems are designed to provide scalable performance, flexibility, and efficiency across modern AI workloads.
Job Summary
We are looking for an experienced Physical Design Engineer (8-14 Years) with solid expertise in RTL-to-GDS implementation, Cadence Innovus, advanced-node Block/SoC designs, and PPA optimization. Candidates should have hands-on System Verilog + Python/Perl scripting experience and a proven track record of delivering high-volume shipped products.
What You'll Drive & Bring to the Role
- Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes
- Expertise and experience with industry-standard CAD tools from Cadence-Innovus.
- Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets.
- Expert knowledge of System Verilog, as well as Perl, Python or other scripting languages.
- Worked at Subsystem level and good experience at Hierarchy block/s.
- Proven track record of execution on products which have shipped in high-volume.
Required Qualifications
• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline with 8-14 yrs of work experience.
Why Join Us?
- World-First Innovation: Opportunity to contribute directly to the development of the world's first OPU™ (Omni