RTL / Verilog Design Engineer (FPGA) (Bengaluru)

RTL / Verilog Design Engineer (FPGA) (Bengaluru)

16 Aug
|
V3Novus Private
|
Bengaluru

16 Aug

V3Novus Private

Bengaluru

RTL / Verilog Design Engineer (FPGA) :

We are seeking an RTL / Verilog Design Engineer (fresher to 3 years of experience) to develop FPGA-based digital logic for our signal processing, navigation, timing and control products. You will design, simulate, verify and implement RTL for high-pin-count FPGAs used in GNSS receivers, beacon receivers, time servers and antenna control systems.

Key Responsibilities
- Design and develop RTL modules in Verilog/VHDL for FPGA-based products — interface controllers, timing logic, data acquisition and signal processing blocks.
- Develop testbenches and perform functional simulation and verification of RTL designs (ModelSim/Vivado Simulator/Questa).
- Perform synthesis, place-and-route, timing constraint definition (SDC/XDC) and timing closure on Xilinx/Intel FPGA platforms (Vivado/Quartus).
- Implement and integrate interface logic such as UART, SPI, I2C, GPIO, memory controllers (DDR), Ethernet MAC and high-speed serial interfaces.
- Integrate and validate soft processor cores (MicroBlaze/NIOS) and IP cores,



and support hardware-software co-design with the firmware team.
- Support FPGA board bring-up and hardware validation using ChipScope/ILA, oscilloscopes and logic analyzers.
- Develop DSP blocks (filters, correlators, NCOs, mixers) for GNSS/beacon signal processing applications under guidance of senior engineers.
- Document design architecture, verification plans, test reports and release notes.

Required Skills:
- Robust fundamentals in digital design — combinational/sequential logic, FSMs, FIFOs, clock domain crossing and pipelining.
- Good hands-on knowledge of Verilog (or VHDL) coding for synthesis and simulation.
- Familiarity with FPGA design flow: simulation, synthesis, implementation, constraints and timing analysis.
- Exposure to Xilinx Vivado or Intel Quartus toolchains.
- Understanding of common peripheral interfaces (UART, SPI, I2C) and memory basics.
- Ability to write testbenches and debug simulation waveforms.

📌 RTL / Verilog Design Engineer (FPGA) (Bengaluru)
🏢 V3Novus Private
📍 Bengaluru

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