Role: Lead Physical Design
This is senior-level position for physical verification who will work on SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/IP/Blocks.
Key Responsibilities
Expertise in physical verification (LVS, ERC/PERC, DFM, OPC, Tape Out process) of SoC/Full-chip-level and/or block-level
Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
Experience in developing sign-off methodology/flow to and supporting a larger team
Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
Expert in EDA Tools: Mentor (Calibre), Synopsys (ICV)
Experience with ERC rules, PERC rules, ESD rules has an added advantage
Robust communication skills, problem solving and analytical skills
Academic Credentials
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering