Infra IP Design Verification Sr Lead Engineer (Noida)

Infra IP Design Verification Sr Lead Engineer (Noida)

16 Aug
|
Qualcomm
|
Noida

16 Aug

Qualcomm

Noida

Company:

Qualcomm India Private Limited
Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering,



or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

We are looking for a Design Verification Sr Engineer / Lead Engineer to drive end-to-end verification of complex IP designs, with a focus on NOC verification . This role requires robust hands-on expertise in SystemVerilog, UVM, and AMBA protocols , along with the ability to lead teams, manage multiple projects, and drive verification excellence .

Key Responsibilities
- Lead verification strategy, planning, and execution for IP/SoC subsystems
- Architect and develop scalable UVM-based environments
- Build and oversee testbench components (agents, scoreboards, monitors, sequences, coverage models)
- Drive coverage closure (functional + code) and signoff
- Lead debug and root-cause analysis across RTL

📌 Infra IP Design Verification Sr Lead Engineer (Noida)
🏢 Qualcomm
📍 Noida

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