Company Description EdgeSilica Private Limited is a semiconductor services company delivering high-quality VLSI design and engineering solutions to global customers. The organization specializes in physical design, design verification, SoC and IP integration, and system software, supporting startups, fabless companies, and product organizations across the semiconductor ecosystem. Teams work with industry-standard EDA tools and adhere to best practices in design quality, scalability, and confidentiality.

EdgeSilica emphasizes robust technical depth, process-driven execution, and flexible engagement models to build long-term, quality-focused partnerships. The company’s mission is to provide reliable, scalable, and future-ready semiconductor engineering services.

Role Description The Design For Test (DFT) Engineer role is a full-time, on-site position based in Hyderabad. The DFT Engineer will design and implement test architectures and strategies for complex digital and mixed-signal ICs, ensuring testability, high coverage, and robust fault detection. Day-to-day responsibilities include developing and integrating scan, BIST, and boundary scan structures, generating test patterns, analyzing coverage reports, and optimizing test flows.

The role involves close collaboration with design, verification, and physical design teams to incorporate DFT requirements early in the design cycle and to support silicon bring-up, characterization,



and production testing. The DFT Engineer will also participate in test plan creation, debug of test failures, documentation of methodologies, and continuous improvement of test processes and tools.

Qualifications

- Strong foundation in Test Engineering and Testing concepts, including fault models, coverage metrics, and test methodologies.
- Proficiency in Test Design and DFT techniques such as scan insertion, ATPG, BIST, and boundary scan.
- Background in Electrical Engineering or related discipline, with understanding of digital logic, CMOS fundamentals, and IC design flows.
- Experience working with Test Equipment and ATE environments, including pattern generation, debug, and correlation between simulation and hardware.
- Hands-on experience with industry-standard EDA tools for DFT and ATPG (e.g., Synopsys, Cadence, or Mentor tools).
- Ability to read and interpret RTL, gate-level netlists, and timing constraints, and collaborate effectively with front-end and back-end design teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
- Strong analytical, problem-solving, and documentation skills, with attention to detail and a commitment to design and test quality.
- Good communication and teamwork capabilities, with the ability to work in a fast-paced, project-driven environment.
- 3+years Experience

📌 Test Design Engineer (Hyderabad)
🏢 EdgeSilica Private
📍 Hyderabad