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We are looking for an experienced Lead Engineer Design Verification with strong expertise in Design Verification, SystemVerilog, UVM, and low-power verification methodologies.

The ideal candidate will have hands-on experience working with power domains, power intent, UPF/CPF, low-power modes, and coverage-driven verification for complex semiconductor designs.

This role involves owning end-to-end verification activities, including testbench architecture, test-plan development, testcase creation, assertions, functional and assertion coverage, power-aware verification, and RTL/UPF debugging.

The candidate will work closely with RTL, architecture, physical design, and other cross-functional teams to ensure high-quality and production-ready silicon.

Key Responsibilities:

- Own end-to-end Design Verification activities for complex SoC/IP designs with a strong focus on low-power functionality.
- Understand and verify power domains, isolation strategies, retention mechanisms, level shifters, power states, and power intent.
- Develop, review, and execute comprehensive verification plans covering functional, low-power, corner-case, and power-state scenarios.
- Work extensively with UPF/CPF specifications and validate implementation of power intent at the RTL and gate-level stages.
- Develop and enhance SystemVerilog/UVM-based verification environments, including reusable agents, drivers, monitors, scoreboards, sequences, and reference models.
- Develop comprehensive testcases for power-up, power-down, sleep, retention, isolation, voltage scaling, and different low-power operating modes.
- Write and maintain SystemVerilog Assertions (SVA) to verify functional and power-management requirements.
- Drive functional coverage, code coverage, assertion coverage, and power-state coverage closure.
- Analyze coverage gaps and develop additional tests, constraints, assertions, and stimulus to achieve verification goals.
- Perform detailed debugging of RTL, testbench, UPF/CPF, assertions,



and simulation failures.
- Debug complex low-power issues involving power-domain crossings, isolation, retention, reset sequencing, and power-state transitions.
- Work with RTL designers and architects to identify design issues, clarify specifications, and resolve functional and low-power verification challenges.
- Collaborate with physical design and implementation teams to ensure power intent is correctly interpreted and implemented across the design flow.
- Participate in verification architecture reviews, test-plan reviews, coverage reviews, and sign-off activities.
- Mentor junior and mid-level verification engineers and provide technical guidance on UVM, SystemVerilog, assertions, and low-power verification.
- Evaluate and introduce advanced Design Verification methodologies, automation, and reusable verification components to improve productivity and quality.
- Contribute to verification sign-off and ensure all functional and low-power verification objectives are met before tape-out.

Technical Skills:

- Strong expertise in SystemVerilog and UVM-based verification methodologies.
- Hands-on experience with low-power design verification and power-aware simulation.
- Strong understanding of UPF (Unified Power Format) and/or CPF (Common Power Format).
- Positive understanding of power domains, isolation cells, retention cells, level shifters, power gating, and power-state transitions.
- Strong experience in developing verification environments, testbenches, testcases, sequences, monitors, scoreboards, and assertions.
- Expertise in SystemVerilog Assertions (SVA)



and coverage-driven verification.
- Strong understanding of functional, code, assertion, and coverage closure methodologies.
- Experience debugging RTL and power-intent-related issues using simulation and waveform analysis.
- Good understanding of RTL design concepts, SoC architecture, clock/reset architecture, and low-power design principles.
- Experience with industry-standard simulation and verification tools.
- Strong scripting/programming skills using languages such as Python, Perl, or Tcl for verification automation is preferred.
- Knowledge of formal verification or emulation-based verification methodologies is an added advantage.

Key Qualifications :

- 6+ years of experience in semiconductor Design Verification, with significant experience in leading verification activities.
- Strong hands-on experience in SystemVerilog, UVM, assertions, and coverage-driven verification.
- Proven experience in low-power verification using UPF and/or CPF.
- Experience working on complex SoC, ASIC, processor, connectivity, or other semiconductor designs.
- Strong debugging and problem-solving skills across RTL, testbench, and power-intent environments.
- Ability to independently own verification deliverables and drive projects through verification sign-off.
- Strong communication and cross-functional collaboration skills.
- Experience mentoring engineers and providing technical leadership within a DV team.

Good to Have:

- Experience with advanced low-power architectures and complex power-management schemes.
- Exposure to gate-level simulation and power-aware GLS.
- Experience with formal verification, emulation, or acceleration platforms.
- Understanding of CDC/RDC verification and its interaction with low-power design.
- Experience developing reusable verification frameworks and methodology improvements.
- Exposure to semiconductor tape-out and silicon bring-up activities.

📌 Silicon Labs - Lead Engineer - Design Verification (India)
🏢 Silicon Labs
📍 India