Company Description LeadIC Design Pvt Ltd accelerates semiconductor innovation through full-stack VLSI engineering expertise, supporting the complete chip development lifecycle for global semiconductor companies. Founded in 2018, the company has grown into a trusted partner known for deep technical capability, strong execution ownership, and flexible engagement models. With engineering teams across India and Canada, LeadIC delivers high-quality design services tailored to product-driven teams.

Its capabilities span custom, memory and analog layout, analog/mixed-signal design, digital design and RTL, verification, physical design, STA, DFT, and IP characterization. LeadIC is recognized for its ownership-driven engineering culture, quality-focused methodologies, and long-term partnerships that help accelerate silicon success.

Role Description This is a full-time, on-site Memory Layout role based in Bengaluru South, requiring a minimum of 4 years of relevant experience. The role involves designing and implementing memory layouts that meet performance, area, reliability, and manufacturability targets, in close collaboration with circuit design and physical design teams.

Responsibilities include creating and optimizing custom memory cells and arrays, performing layout verification (DRC/LVS), and ensuring compliance with foundry design rules and process requirements.



The position also includes debugging layout-related issues, supporting tape-out activities, documenting layout methodologies, and contributing to continuous improvement of internal design flows and best practices.

Qualifications

- Robust expertise in Layout Design for memory and custom circuits, with hands-on experience in deep submicron technologies.
- Ability to work with Page Layout and Graphics tools relevant to IC layout visualization and documentation.
- Familiarity with Graphic Design and Graphics concepts for creating clear technical diagrams, schematics, and layout views.
- Exposure to Digital Marketing is a plus for supporting technical content, presentations, and internal/external communication.
- 4+ years of experience in memory or custom layout within the semiconductor/VLSI industry.
- Proficiency with industry-standard EDA tools (e.g., Cadence Virtuoso, Synopsys, Mentor) and layout verification flows (DRC/LVS).
- Solid understanding of CMOS processes, device physics, and design rules for advanced technology nodes.
- Attention to detail, strong problem-solving skills, and ability to collaborate effectively in cross-functional engineering teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field, or equivalent practical experience.

📌 Memory Layout - 4+ Years - Bangalore Location (Bengaluru)
🏢 leadIC Design
📍 Bengaluru