As a DFT Engineer at Nsemi, you will be responsible for designing and implementing Design-for-Test strategies to ensure the highest quality and reliability of our semiconductor products. Your expertise in scan insertion, ATPG, and MBIST will be crucial in optimizing test coverage and enhancing silicon debug processes. You’ll collaborate closely with cross-functional teams to deliver robust and efficient test solutions, playing a vital role in the success of our cutting-edge projects.

Design For Testability DFT - Engineer

As a DFT Engineer at Nsemi, you will be responsible for designing and implementing Design-for-Test strategies to ensure the highest quality and reliability of our semiconductor products. Your expertise in scan insertion, ATPG, and MBIST will be crucial in optimizing test coverage and enhancing silicon debug processes. You’ll collaborate closely with cross-functional teams to deliver robust and efficient test solutions, playing a vital role in the success of our cutting-edge projects.

Design For Testability DFT - Engineer

As a DFT Engineer at Nsemi, you will be responsible for designing and implementing Design-for-Test strategies to ensure the highest quality and reliability of our semiconductor products. Your expertise in scan insertion, ATPG, and MBIST will be crucial in optimizing test coverage and enhancing silicon debug processes. You’ll collaborate closely with cross-functional teams to deliver robust and efficient test solutions, playing a vital role in the success of our cutting-edge projects.

Qualification Required Qualification Required:

- Typically requires minimum of 3+ years of experience in DFT on high complexity SoC designs.




- Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.
- Typically requires minimum of 3+ years of experience in DFT on high complexity SoC designs.
- Bachelors OR Master’s Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities Roles And Responsibilities:

- 3+ Experience in complex SOC level DFT execution in advanced finFET technology.
- Robust DFT fundamental knowledge from defect models to ATPG algorithm.
- Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
- Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes
- 3+ Experience in complex SOC level DFT execution in advanced finFET technology.
- Strong DFT fundamental knowledge from defect models to ATPG algorithm.
- Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
- Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes

Required Technical And Professional Expertise Required Technical And Professional Expertise:

- Excellent communication and interpersonal skills.
- Strong and effective presentation skills, able to operate at multiple levels including senior management.
- Self-motivated.
- Take ownership of problems.
- Creative problem solving.
- Team player
- Excellent communication and interpersonal skills.
- Strong and effective presentation skills, able to operate at multiple levels including senior management.
- Self-motivated.
- Take ownership of problems.
- Creative problem solving.
- Team player

Location:

Location

- Bangalore
- Bangalore

Apply

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📌 Design For Testability DFT - Engineer (Bengaluru)
🏢 Nsemi Design Services India
📍 Bengaluru