- 5 to 10 years of ASIC/SoC Design Verification experience.
- Expertise in SystemVerilog (SV) and UVM.
- Solid C programming skills.
- Experience in RTL and Gate-Level Simulation (GLS) debug.
- Experience in constrained-random verification, functional coverage, and SystemVerilog Assertions (SVA).
- Strong debugging skills with Verdi/DVE / SimVision.
- Experience in Wi-Fi and/or Low Power Wireless (BLE, Zigbee, Thread, Matter) verification.
- Ability to debug protocol, subsystem and SoC-level failures independently.
- Good understanding of digital design fundamentals and SoC architecture.
Preferred candidate profile:
- RF interface debug and digital/RF integration knowledge.
- PHY/MAC architecture understanding.
- DSP fundamentals and communication systems knowledge.
- MATLAB/Simulink exposure for algorithm understanding.
- Python scripting for automation.
- Experience with VCS/Xcelium/Questa, Git and Jenkins.
- Experience with CDC/RDC and SDF timing debug ($setuphold, $recrem).
- Develop and maintain UVM verification environments.
- Develop test plans, test cases, sequences, scoreboards and assertions.
- Execute RTL and GLS regressions and conduct root cause analysis.
- Debug RF interface, protocol and integration issues.
- Work closely with RTL, Firmware, Architecture and Validation teams.
- Drive closure of verification issues with high quality.