SRAM Memory Layout Engineer

Experience: 3–6 Years
Location: Bangalore
Notice Period: Immediate to 60 Days
Technology: TSMC 2nm/3nm | Samsung 2nm/4nm

Job Description
We are looking for experienced SRAM Memory Layout Engineers with strong hands-on expertise in advanced-node memory layout and physical verification. The ideal candidate should have experience working on SRAM macros and memory structures from layout development through tape-out.

Key Responsibilities & Skills
3–6 years of hands-on experience in SRAM Memory Layout.
Strong experience with Single Port, Dual Port, Pseudo Dual Port SRAM, Register File, FIFO, and Embedded Memory macros.
Hands-on experience with TSMC 2nm/3nm and/or Samsung 2nm/4nm technology nodes.
Develop and integrate bit-cell arrays, sense amplifiers, decoders, column muxes, row/column periphery, and top-level memory blocks.
Experience across the complete layout lifecycle, including floorplanning, placement, routing, optimization, DRC/LVS/ERC, PEX, and tape-out.




Strong knowledge of matching, symmetry, EM/IR, density, antenna, ESD, and advanced-node design rules.
Proficiency in Cadence Virtuoso and Calibre DRC/LVS/PEX.
Experience in area, performance, power, yield, and reliability optimization.
Solid debugging skills with hands-on experience in PV issue resolution and ECO implementation.
Good scripting skills in Tcl/Python for layout automation and flow improvement will be an added advantage.
Ability to collaborate effectively with Memory Design, Circuit Design, and Verification teams.

Preferred Candidate Profile
Strong understanding of advanced-node SRAM layout methodologies.
Good problem-solving and debugging skills.
Ability to independently handle layout tasks and resolve physical verification issues.
Strong communication and cross-functional collaboration skills.

📌 SRAM Memory Layout Engineer (Bengaluru)
🏢 Modernize Chip Solutions (MCS)
📍 Bengaluru