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Experience: 10+ yrs
Location: Bengaluru
Job Type: Full-time
We are looking for an experienced Physical Design Engineer to drive end-to-end physical implementation of complex semiconductor designs. The role involves taking designs from netlist through floorplanning, placement, clock-tree synthesis, routing, timing closure, physical verification, and sign-off.
The ideal candidate will have deep hands-on expertise with Cadence Innovus, robust knowledge of STA, PNR, floorplanning, timing optimization, and physical design methodologies, and the ability to independently handle challenging implementation and closure activities on advanced designs.
Key Responsibilities
Own the end-to-end physical design flow from netlist to final sign-off.
Perform chip/block-level floorplanning, power planning, placement, CTS, routing, and physical optimization.
Use Cadence Innovus for physical implementation, optimization, and PNR activities.




Analyze and resolve timing violations using Static Timing Analysis (STA) techniques.
Work closely with STA teams to achieve timing closure across setup, hold, and other critical timing scenarios.
Optimize designs for performance, power, area, congestion, and signal integrity.
Develop and execute effective floorplanning and partitioning strategies based on design requirements.
Identify and resolve congestion, routing, placement, clock, and physical design challenges.
Support implementation across multiple design stages and ensure smooth progression toward sign-off.
Collaborate with RTL, synthesis, DFT, STA, verification, and physical verification teams to resolve cross-functional issues.
Analyze implementation reports and identify opportunities for improving PPA and overall design quality.
Debug complex physical design issues and drive root-cause analysis and corrective actions.
Contribute to improving physical design flows, methodologies, automation,

📌 Physcial Design Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru