? We’re Hiring Senior RTL (ASIC) Engineers at ACL Digital

Open Requirement:
Experience: 6+ years in RTL Design.
Availability: We are looking for candidates who can join us on a short notice period.

Are you an expert in ASIC front-end design with a passion for building complex SoCs? ACL Digital is expanding its VLSI design team, and we are looking for high-caliber RTL (ASIC) Engineers to join our team.

Who we are looking for:
We are seeking experienced professionals (6+ years) who have a strong foundation in the complete ASIC design flow and can hit the ground running on our current project pipeline.

Core Responsibilities & Technical Skills:
Design & Coding: Robust expertise in RTL coding using Verilog/SystemVerilog and micro-architecture development.
Static Verification: Deep hands-on experience with Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis.
Tools:



Proficient in tools such as Synopsys SpyGlass, Questa, or similar static verification platforms.
ASIC Flow: Knowledge of synthesis, Logical Equivalence Checking (LEC), and full-chip integration.
Protocols: Experience with standard protocols (AMBA AXI/AHB/APB) is highly desirable.

Why Join ACL Digital?
Be part of a high-growth environment working on advanced node (3nm/5nm) semiconductor projects alongside industry leaders. We value technical depth, ownership, and innovative problem-solving.

How to Apply:
Interested candidates, please share your updated resume at [email protected] or reach out via DM for more details.
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📌 Senior RTL Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru