STD Cell Layout Engineer (Bengaluru)

STD Cell Layout Engineer (Bengaluru)

19 Aug
|
Weekday AI
|
Bengaluru

19 Aug

Weekday AI

Bengaluru

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Experience: 4+ yrs

Location: Bengaluru

Job Type: Full time

We are looking for a skilled Semiconductor Design Engineer to contribute to end-to-end chip development programs for global semiconductor projects. The role offers an opportunity to work on technically challenging designs across different stages of the semiconductor development lifecycle, collaborating with experienced engineering teams and contributing to high-quality silicon development.

The ideal candidate will have strong fundamentals in semiconductor design, hands-on experience with relevant design methodologies and tools, and the ability to take ownership of assigned technical deliverables.

Key Responsibilities

- Contribute to semiconductor design and development activities across the chip development lifecycle.
- Understand design specifications and translate requirements into robust technical implementations.
- Develop, modify, and optimize design components based on project requirements.
- Work with cross-functional teams including RTL design, verification, physical design, DFT, validation, and architecture teams.
- Perform technical analysis, debugging, and root-cause investigation of design issues.
- Participate in design reviews and contribute to improving design quality and methodology.
- Use industry-standard EDA tools and semiconductor design flows to execute assigned tasks.
- Develop and maintain technical documentation, design specifications, and project deliverables.
- Support functional verification,



integration, debugging, and issue resolution activities.
- Ensure assigned deliverables meet defined quality, performance, and schedule requirements.
- Collaborate with engineering teams across different locations to ensure effective project execution.
- Stay current with emerging semiconductor technologies, methodologies, tools, and industry practices.
- Contribute to process improvements and automation initiatives that enhance engineering productivity.

What's Makes You a Great Fit
- 4+ years of relevant experience in semiconductor/ASIC/SoC design or a closely related engineering domain.
- Strong understanding of VLSI and semiconductor development methodologies.
- Hands-on experience with one or more areas of chip development such as RTL Design, Verification, Physical Design, DFT, Analog/Mixed Signal, or Design Validation.
- Familiarity with industry-standard EDA tools and design flows.
- Strong analytical and problem-solving capabilities with an ability to debug complex technical issues.
- Good understanding of digital design concepts, semiconductor architectures, and chip development processes.
- Ability to work effectively with cross-functional engineering teams.
- Strong communication and documentation skills.
- Self-driven approach with the ability to take ownership of technical deliverables.
- Comfortable working in a fast-paced, project-oriented engineering environment.
- A bachelor's or master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline is preferred.

📌 STD Cell Layout Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru

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