Role Description

Client Job Title: DFT practice head

UST Job Title: Architect II - VLSI

Who We Are

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

The Opportunity

UST is looking for an experienced DFT Practice Head to lead and grow its Design for Test (DFT) practice. The ideal candidate will bring strong technical expertise in DFT methodologies, proven leadership experience, customer-facing capabilities, and a track record of delivering complex SoC/ASIC programs for global semiconductor customers.

Key Roles & Responsibilities

- Define and drive the overall DFT practice strategy, roadmap, and growth.
- Lead end-to-end delivery of DFT projects across multiple customer engagements.
- Build, mentor, and manage high-performing DFT engineering teams.
- Drive competency development, technical training, and capability-building initiatives.
- Engage with customers to understand requirements and provide effective DFT solutions.
- Oversee project planning, execution, quality, schedules, resource utilization, and risk management.
- Support pre-sales, solution architecture, effort estimation, and proposal preparation.
- Establish and improve DFT methodologies, best practices, and quality standards.
- Collaborate closely with RTL Design, Verification, Physical Design, ATPG, Product Engineering, and Program Management teams.
- Drive hiring, resource planning, utilization, and career development for the DFT practice.
- Manage customer relationships, regular reviews, issue resolution, and overall customer satisfaction.




- Drive innovation and evaluate new DFT technologies, methodologies, and EDA tools.

Required Skills

- Strong expertise in DFT architecture and implementation for complex SoCs/ASICs.
- Hands-on experience with Scan Insertion, Scan Compression, MBIST, LBIST, Boundary Scan/JTAG (IEEE 1149.x), ATPG, and Diagnosis.
- Strong understanding of RTL Design, Synthesis, STA, and Physical Design flows.
- Experience with low-power DFT, test compression, and hierarchical DFT methodologies.
- Experience with industry-standard DFT/EDA tools such as Synopsys TestMAX/DFT Compiler, Cadence Modus, and Siemens Tessent.
- Strong scripting skills in Tcl, Perl, Python, or Shell.
- Proven experience in leading DFT teams and delivering complex semiconductor programs.
- Strong customer-facing, communication, stakeholder management, and leadership skills.

Desired Skills

- Experience with silicon bring-up, failure analysis, diagnosis, and yield improvement.
- Experience working with global semiconductor customers.
- Solid experience in DFT practice development, pre-sales, solutioning, estimation, and proposal preparation.
- Experience driving DFT innovation and adoption of new methodologies and EDA tools.
- Exposure to end-to-end SoC/ASIC development and cross-functional semiconductor engineering teams.

Qualification

- Bachelor's or Master's degree in Electronics/Electrical Engineering, Microelectronics,



VLSI, or a related field.
- 15+ years of relevant experience in DFT/ASIC/SoC engineering, with significant experience in technical and people leadership.

What We Believe We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.

Humility We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity Through business, we will better the lives of those less fortunate than ourselves.

Integrity We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation. All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law. UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

- To support and promote the values of UST.
- Comply with all Company policies and procedures

Skills DFT, SoC Architecture, Tcl, Perl

📌 Architect II - VLSI (Bengaluru)
🏢 UST
📍 Bengaluru