Lead STA Engineer

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Bangalore /Hyderabad/Kochi

Role Overview

As a Lead STA Engineer(preferably 7+Yrs Experience ), you will be responsible for ensuring timing closure and sign-off for complex System-on-Chip/Subsystem designs. This involves analyzing, validating, and optimizing timing across multiple design hierarchies and technology nodes to meet performance, power, and reliability targets.

Key Responsibilities

Static Timing Analysis (STA)

Perform STA at block and full-chip levels across multiple corners, modes, and conditions using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).

Timing Constraints Development

Create and validate SDC constraints for hierarchical SoC designs, including clocking, multi-mode, and multi-corner scenarios.

Timing Closure

Drive timing closure during synthesis, place-and-route, and sign-off stages. Generate timing ECOs and collaborate with physical design teams for optimization.





Cross-Functional Collaboration:

Work closely with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues and ensure design quality.

Automation & Scripting:

Develop scripts (Tcl, Python, Perl) to automate STA flows, reporting, and constraint validation.

Advanced Analysis

Handle OCV (On-Chip Variation), noise, crosstalk, and derate methodologies for accurate timing sign-off.

Documentation & Reviews:

Maintain STA methodology documents and participate in design reviews.

Mentorship

Guide junior engineers on STA techniques and best practices.

Required Skills & Tools

Robust understanding of digital design principles, clocking, and timing concepts.

Skills

Tempus

Primetime

SoC

SDC

MMMC

ECO

OCV

Con tact

Uday muday_bhaskar@yahoo .com

Mulya Technologies

"Mining the Knowledge Commun ity"

📌 STA Lead Engineer (Hyderabad)
🏢 Mulya Technologies
📍 Hyderabad