20 Aug
|
ACL Digital
|
Bengaluru
20 Aug
ACL Digital
Bengaluru
Hi All,
Job Location: Bangalore
Notice Period: 15 days to 30 Days
Minimum: 5+ Years
1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.
- Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
- Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
- Experience with hardware architecture exploration, performance modelling will be a big plus.
- Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.
6.Must have experience in Lint and CDC.
7.Must have RTL Design worked on PCIe/CXL
Thanks,
K Himabindu
📌 Senior RTL Design Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru