Job Summary

We are looking for an experienced
DFT Engineer
with
5+ years of hands-on experience
in Design-for-Test (DFT) implementation and verification for complex ASIC/SoC designs. The ideal candidate should have solid expertise in scan insertion, ATPG, MBIST, JTAG/IJTAG, DFT verification, and test pattern generation/validation.

The candidate will be responsible for executing DFT activities from specification and architecture through implementation, verification, pattern generation, and sign-off.

Key Responsibilities
Develop and implement DFT architecture for complex ASIC/SoC designs.
Perform
scan insertion, scan compression, ATPG, and test pattern generation
.
Work on
MBIST/LBIST
implementation and verification.
Implement and debug
JTAG, IJTAG, boundary scan, and test access mechanisms
.
Develop and validate DFT constraints and ensure DFT rule compliance.
Perform DFT simulations and debug test-related issues.
Validate ATPG patterns and analyze fault coverage.
Work closely with RTL, Design Verification, Physical Design, STA,



and other teams to resolve DFT-related issues.
Support DFT integration at block and full-chip levels.
Analyze and improve
stuck-at, transition, and other fault coverage metrics
.
Debug scan chain, compression, clock, reset, and test-mode issues.
Support DFT timing and physical implementation requirements.
Participate in DFT sign-off activities and provide required reports and documentation.
Automate DFT flows and reporting using
TCL, Perl, Python, or Shell scripting
.
Support post-silicon test/debug activities when required.

Required Skills
5+ years of relevant DFT/ASIC experience
.
Strong hands-on experience with:
Scan insertion
ATPG
Scan compression
MBIST
JTAG / IJTAG
Boundary Scan
DFT verification
Positive understanding of
ASIC/SoC design and DFT methodologies
.
Experience with DFT tools from
Synopsys, Cadence, Siemens EDA/Mentor
, or equivalent.
Solid knowledge of ATPG fault models an

📌 Dft Engineer Bengaluru (India)
🏢 SmartSoC Solutions
📍 India