Drive timing closure at the sub-block level for AMS/IP macros.
Perform Static Timing Analysis (STA) and resolve timing-related issues.
Develop and maintain timing models and Liberty (.lib) characterization.
Analyze timing paths, constraints, topology, and generate timing reports.
Support timing signoff activities and design optimization.
Collaborate with design and characterization teams.
Improve STA methodologies through automation and scripting.
Key Deliverables:
Timing models for AMS/IP macros.
STA, timing path, and signoff analysis reports.
Timing closure recommendations and design fixes.
Automation solutions to enhance STA productivity and flow efficiency.
Required Skills & Experience:
Hands-on experience in STA and Liberty (.lib)



characterization of AMS/IP macros.
Solid understanding of STA concepts and timing fundamentals.
Experience with HSPICE/Spectre is an added advantage.
Proficiency in Shell, Perl, Tcl, and/or Python scripting.
Robust analytical, debugging, and problem-solving skills.
Valuable communication, collaboration, and documentation skills.
Detail-oriented and methodical approach.
Qualification:
Master's Degree or equivalent.
Experience:
Relevant experience in AMS/IP Timing Analysis and Characterization.

📌 Engineer Bengaluru
🏢 L&T Technology Services
📍 Bengaluru