Job DescriptionRTL Design Engineer | 5-12 Years
nWe are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.
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nKey Requirements:
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- Strong experience in RTL design using Verilog/SystemVerilog or VHDLn
- Hands-on experience in ASIC/SoC developmentn
- Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMsn
- Experience in functional verification and RTL debuggingn
- Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.n
- Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cyclen

nGood to Have:
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- Exposure to UVM-based verification environmentsn
- Experience with Python, Perl, or Shell scriptingn
- Familiarity with STA and synthesis flowsn

nQualification:
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- Bachelor‘s or Master‘s degree in Electrical Engineering, Electronics, Computer Engineering, or a related fieldn

nWhy Join Us?
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- Opportunity to work on cutting-edge ASIC/SoC technologiesn
- Collaborative and fast-paced engineering environmentn
- Solid learning and career growth opportunitiesn
- Competitive compensation and benefits packagen

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📌 RTL Design Engineer Role (Jharkhand)
🏢 HCLTech
📍 Jharkhand