20 Aug
|
Ciliconchip
|
Bengaluru
20 Aug
Ciliconchip
Bengaluru
Key Requirements:
Methodologies: Solid hands-on UVM / OVM and SystemVerilog (Constrained-Random Verification)
Assertions & Coverage: SystemVerilog Assertions (SVA) & Functional Coverage modeling
Protocols (Any): PCIe, USB, DDR, or Ethernet
EDA Tools: Xcelium, VCS, or Questa
Debug Tools: Verdi or SimVision
Scripting: Python, Perl, or TCL
What You'll Do:
Lead IP/subsystem verification, build UVM environments (monitors, scoreboards, drivers), track coverage closure, run regressions, and mentor junior engineers.
📌 Senior Design Verification Engineer (Bengaluru)
🏢 Ciliconchip
📍 Bengaluru