Staff Physical Design Engineer
Location: Bengaluru
Experience: 8–12 Years
Role Overview
We are looking for a Staff Physical Design Engineer with strong hands-on expertise in full-chip physical implementation, timing closure, and signoff for complex SoC designs.
Key Responsibilities
Own full-chip RTL-to-GDSII implementation across synthesis, floorplanning, placement, CTS, routing and signoff.
Drive MCMM STA, setup/hold closure, ECOs and critical path optimization.
Resolve congestion, IR/EM, signal integrity, DRC/LVS and physical design issues.
Optimize PPA, timing, power and area across implementation stages.
Collaborate with RTL, STA, DFT, PD and signoff teams to drive tapeout readiness.
Develop and enhance PD flows and automation using Tcl/Python/Perl.
Core Technical Skills




Strong full-chip Physical Design / ASIC implementation experience.
Hands-on with Synopsys ICC2/Fusion Compiler, PrimeTime, Design Compiler or equivalent.
Deep understanding of STA, MCMM, CTS, timing closure and ECO methodology.
Strong expertise in floorplanning, power planning, placement and routing.
Experience with advanced-node SoCs and complex clocking architectures preferred.
Robust scripting and debugging skills.
Ideal Candidate: A highly hands-on Physical Design engineer who can independently drive full-chip implementation and timing closure through tapeout.

📌 Staff Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru