? Hiring: Gate Level Simulation (GLS) – Design Verification Engineer
We are looking for experienced Design Verification (DV) Engineers to work on complex ASIC / SoC / IP verification projects.
? Experience: 7–10 Years
? Minimum GLS Experience: 5+ Years
? Locations: Bengaluru | Vizag | Kochi | Ahmedabad
? Hiring Mode: Subcon / FTE
? Qualification: B.E./B.Tech/M.E./M.Tech in Electrical/Electronics Engineering
? Key Responsibilities
• Develop directed and constrained-random test cases
• Perform RTL and Gate Level Simulations
• Debug failures and root-cause issues across RTL, testbench and tools
• Develop scalable verification environments
• Automate regression flows and improve verification productivity
• Collaborate with Design, Architecture and Physical Design teams
?️ Required Skills




• Robust knowledge of SystemVerilog
• Hands-on experience with UVM
• Experience with VCS / Verdi or similar EDA tools
• Strong experience in RTL & Gate Level Simulation debugging
• Good knowledge of PCIe protocol
• Proficiency in Python / Perl / Shell scripting
• Strong understanding of ASIC/SoC/IP Design Verification
? Interested candidates can share their updated resumes to [email protected]
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📌 Gate Level Simulation (Bengaluru)
🏢 Headway Tek
📍 Bengaluru