ASIC Front-end Design engineer (5-12 Years)

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills.

You will have a significant prospect to interact with system design teams across geographies.

Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Define and architect high-performance blocks for the latest,



most advanced networking ASICs

Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power

Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

Strong Verilog RTL coding skills

Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable

Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus

Knowledge of high performance memory subsystems

experience range 5-12 years

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

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