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Experience: 3+ yrs
Location: Bengaluru, Karnataka, India
Job Type: Full-time
We are looking for an experienced Physical Verification / Layout Verification Engineer to support the verification and sign-off of complex VLSI designs. The role involves ensuring physical layouts meet foundry design rules and are electrically and physically consistent with the intended design before tape-out.
The ideal candidate will have robust hands-on expertise in DRC, LVS, ERC, antenna, density checks, and physical verification, with practical experience debugging complex layout issues and supporting block/IP-level sign-off.
Key Responsibilities
Perform physical verification and layout verification for VLSI designs at block, IP, and chip levels.
Execute and analyze DRC, LVS, ERC, antenna, and density checks using industry-standard verification tools.
Work extensively with Siemens Calibre or equivalent physical verification platforms.
Debug and resolve complex LVS shorts, opens, device mismatches,



connectivity issues, and extraction errors.
Analyze DRC and other rule violations and work with layout teams to drive timely closure.
Review layout connectivity and ensure consistency between schematic/netlist and physical implementation.
Support block/IP-level physical sign-off and tape-out activities.
Collaborate with layout, circuit design, technology, and CAD teams to resolve verification issues.
Analyze extracted devices and parasitic information where required for verification and debugging.
Ensure layouts comply with applicable foundry design rules and CMOS technology requirements.
Develop and maintain scripts and utilities using Perl, Python, Shell, or TCL to automate repetitive verification and reporting activities.
Improve physical verification workflows, methodologies, and turnaround time through automation.
Track verification status, identify critical issues, and communicate progr

📌 Physical verification Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru