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Role Summary
Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects.
Key Responsibilities
Own end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies.
Develop, certify,



and maintain PnR implementation flows across technology nodes and design styles.
Drive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure.
Define implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure.
Develop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness.
Partner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues and improve project execution.
Enable new technology nodes, validate EDA tool features, and drive methodology enhancements for future projects
Required Qualifications
Bachelor's/Master's degree in Electrical/Electronics Engineering.
Strong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification.
Expertise in clock-tree synthesis, clock skew/laten

📌 Physical Design Engineer (Bengaluru)
🏢 Advanced Micro Devices
📍 Bengaluru