Job Description

1. Develop comprehensive verification plans based on design and architecture specifications.
2. Build scalable and reusable UVM-based verification environments from scratch.
3. Develop test cases, sequences, scoreboards, monitors, checkers, and coverage models.
4. Perform block-level, subsystem-level, and SoC-level verification.
5. Create constrained-random and directed test scenarios using SystemVerilog/UVM.
6. Perform functional and code coverage analysis and drive closure.
7. Debug RTL issues and collaborate closely with design, architecture, and validation teams.
8. Analyze simulation failures and provide root-cause analysis.
9. Participate in design and verification reviews.
10. Support regression execution and automation activities.

Technical Skills
- Strong experience in SystemVerilog and UVM.
- Hands-on experience in developing verification environments from scratch.
- Expertise in constrained-random verification methodologies.




- Experience with assertions (SVA).
- Robust debugging skills using industry-standard simulators.
- Knowledge of coverage-driven verification.
- Experience with RTL verification of complex digital designs.

Tools & Technologies
- Simulators: VCS, Xcelium, QuestaSim, or equivalent.
- Debug Tools: Verdi, DVE, SimVision.
- Version Control: Git/Perforce.
- Scripting: Python, Perl, Tcl, or Shell scripting.

Preferred Skills
- Experience in SoC/IP verification.
- Knowledge of AMBA protocols such as AXI, AHB, APB.
- Experience with DDR, PCIe, USB, Ethernet, or other high-speed protocols.
- Exposure to Formal Verification is a plus.
- Understanding of low-power verification (UPF/CPF).
- Experience with emulation or FPGA prototyping is an advantage

📌 Design Verification Engineer (Bangalore Metropolitan Area)
🏢 Ad Astra Consultants
📍 Bangalore Metropolitan Area