As a member of the CT India physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design implementation team, you will work closely with the SOC architects, Physical design architects, design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to lead design implementation and convergence activities in the backend from a PnR implementation perspective.
In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance IP, Test chip and Chiplet designs. This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes.
THE PERSON:
You will be responsible for driving a team of silicon design engineers for the successful delivery of project tape-outs from RTL-GDS.
You will use your knowledge of Physical design to lead a complete set of Backend activities, Specifically PnR, timing,
verification and signoff including IP integration and full-chip aspects.
This position requires a detail-oriented candidate, who possesses good communication skills and can handle/work with teams.
KEY RESPONSIBILITIES:
- Lead Physical design team for implementation and convergence of highly complex tiles
- Will be responsible for delivery of GDS starting from RTL including Signoff and physical verification.
- Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA.
- Valuable understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows.
- Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle.
- Drive methodology development ide