Job Description RTL Design Engineer | 5-12 Years
n We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.
n

n Key Requirements:
n n Strong experience in RTL design using Verilog/SystemVerilog or VHDL
n Hands-on experience in ASIC/SoC development
n Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
n Experience in functional verification and RTL debugging
n Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.
n Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle
n n Good to Have:




n n Exposure to UVM-based verification environments
n Experience with Python, Perl, or Shell scripting
n Familiarity with STA and synthesis flows
n n Qualification:
n n Bachelor‘s or Master‘s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field
n n Why Join Us?
n n Opportunity to work on cutting-edge ASIC/SoC technologies
n Cooperative and fast-paced engineering environment
n Strong learning and career growth opportunities
n Competitive compensation and benefits package
n n

📌 RTL Design Engineer Role (Ranchi)
🏢 HCLTech
📍 Ranchi