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- Test architecture definition.
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- Identifying and implementing RTL changes for DFT.
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- Performing scan insertion, LEC checks, low power CLP checks.
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- Developing timing constraints for test mode timing closure.
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- Scan and ATPG for different fault models.
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- Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
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- IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
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- Running zero delay and timing simulations and debugging on all the above aspects.
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- Supporting post silicon bring up.
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- Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
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- Experience working on very high speed and low power designs
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📌 Lead DFT design Engineer (Bengaluru)
🏢 Cadence System Design and Analysis
📍 Bengaluru
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